64-bit Calculator

Designed a fully synthesizable 64-bit unsigned addition system as the SiliconJackets Digital Design onboarding project. The system performs 64-bit addition using a 32-bit datapath by splitting each operation into lower and upper halves with carry propagation — a real-world technique used in area-constrained designs where a full 64-bit adder would be too expensive.

The architecture consists of four core modules: a 7-state FSM controller that orchestrates the computation lifecycle, a 32-bit ripple-carry adder (adder32) built from individual full-adder cells, a dual-port result buffer that stores lower and upper halves of the 64-bit result, and a top-level integration module (top_lvl) that connects two ChipFoundry 1024×32 SRAM macros for operand storage and result write-back.

The FSM controller cycles through S_IDLE → S_READ_A → S_READ_B → S_CALC_LO → S_CALC_HI → S_WRITE → (repeat or S_END). During S_READ_A and S_READ_B, it issues memory reads with proper 1-cycle SRAM latency handling — operand A is captured one cycle after its read is issued (in S_READ_B), and operand B is captured similarly in S_CALC_LO. The carry-out from the lower 32-bit addition is latched into carry_store and fed as carry-in during the upper computation.

The SRAM interface is dual-banked: SRAM A stores lower 32-bit words and SRAM B stores upper 32-bit words. Both share the same address bus and control signals (enable, read/write-bar). The controller splits the 64-bit write data bus and combines the two 32-bit read data outputs transparently. Address pointers auto-increment by 2 for reads (consecutive operand pairs) and by 1 for writes, with the FSM terminating when the write pointer reaches write_end_addr.

All RTL was written using fully synthesizable constructs: always_ff for sequential logic with non-blocking assignments, always_comb for purely combinational logic, and proper use of unique case to prevent latch inference. Waveform-level debugging with SimVision revealed a subtle timing issue in the carry propagation path that required careful synchronization between the SRAM read latency and the combinational adder output.