Class-Based Testbench

Built a complete class-based verification environment for the 64-bit calculator DUT (top_lvl), following UVM-style methodology. The testbench architecture includes a driver (calc_driver), monitor (calc_monitor), scoreboard (calc_sb), transaction class (calc_seq_item), and sequencer (calc_sequencer) — all parameterized on DataSize and AddrSize for portability.

The scoreboard implements a golden reference model that maintains shadow copies of both SRAMs (mem_a and mem_b). On each read transaction, it stores operand values and computes the expected 64-bit sum including carry propagation between the lower and upper 32-bit halves. On write transactions, it compares the DUT output against the golden model and halts simulation immediately on any mismatch.

Designed 6 directed test cases targeting both functional correctness and corner-case behavior: basic zero+zero addition, MAX+MAX overflow (0xFFFFFFFF + 0xFFFFFFFF), zero+MAX identity, carry propagation from lower to upper word, and multi-result operations (4 reads → 2 writes). Additionally, ran 10 constrained-random transactions generated by the sequencer with constraints ensuring valid, non-overlapping read/write address ranges.

Wrote 4 SystemVerilog Assertions (SVA) embedded in the testbench top module to continuously verify protocol and timing invariants: (1) read/write mutual exclusion — rd_en and wr_en never asserted simultaneously; (2) LSB-before-MSB ordering — S_CALC_HI must always follow S_CALC_LO; (3) carry propagation correctness — carry_store must match carry_out from the prior CALC_LO cycle; and (4) reset behavior — FSM returns to S_IDLE within one clock cycle of reset assertion.

Achieved 99.93% overall verification coverage as measured by Cadence IMC, with 100% instance coverage across all DUT modules (calc_tb_top, calc_if, my_calc), 100% on all 4 assertions, and 99.86% type coverage. The coverage report shows 3,345 out of 3,365 coverage points hit.