RTL-to-GDSII Flow

Executed a complete RTL-to-GDSII physical design flow as part of the SiliconJackets onboarding project, starting from a synthesized netlist and ending with a DRC-clean layout ready for tape-out. The flow used Cadence Genus for synthesis and Innovus for place-and-route, running on a ChipFoundry 45nm process.

Designed the chip floorplan by defining die area sizing, constructing multi-layer power mesh grids, and manually placing SRAM macros (CF_SRAM_1024x32). Each SRAM placement decision had direct consequences on routing congestion, IR drop, and timing — requiring iterative refinement to balance area, power, and performance.

Identified and resolved DRC violations caused by Innovus's automated router drawing metal wires directly across the internal area of the SRAM macros. By analyzing the LEF file, I discovered that most SRAM signal pins sit on the met1 layer, and the OBS (obstruction) block defines no-route zones for met1 and met2 to prevent shorting out internal bitlines and word lines. The router was violating these zones when connecting logic nets to the macro pins.

Fixed the DRC violations by adding met1/met2 routing blockages in the floorplan configuration and defining keep-out margins (halos) around each SRAM macro to push standard cells away from the macro perimeter. This prevented the router from drawing paths over the SRAM's internal metal layers.

Validated the final layout through parasitic RC extraction using Cadence Quantus and performed post-layout Static Timing Analysis with Cadence Tempus. The design achieved timing closure with positive slack across all critical paths, confirming that the physical implementation faithfully preserved the RTL's intended functionality.