AshwanthThiyagarajan

Hey, I'm Ashwanth. I'm a Computer Engineering student at the Georgia Institute of Technology, where I spend my time deep in the world of digital design and hardware verification. There's something deeply satisfying about crafting logic at the register-transfer level and watching it come to life on silicon.

My journey into engineering started with a curiosity about how the devices we use every day actually work — not just the software, but the actual hardware underneath. That curiosity led me to SystemVerilog RTL design, where I've designed everything from FSM controllers to 64-bit datapaths, and design verification, where I've built class-based testbenches achieving 99.93% DUT coverage.

Outside of the lab, I'm a member of SiliconJackets, Georgia Tech's premier chip design club, where I've contributed to full RTL-to-GDSII physical design flows. I also develop iOS applications with the GT iOS Club and have contributed to gravitational wave data analysis research with LIGO/Virgo.

When I'm not writing RTL or debugging waveforms, you'll find me weightlifting, diving into automotive engineering topics, or optimizing systems performance — because efficiency is a mindset, not just a metric.